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  • DDR2 ( H2I1G16KFR-Y5C )

    The H2I1G16KFR is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random- access memory (SDRAM) containing 1024 Mbits in a 16-bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency,Write latency = Read latency -1, Off-Chip Driver (OCD)impedance adjustment, and On Die Termination(ODT).

    DDR2
  • DDR3 ( H3I1G16LFG-PBA )

    The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is double data rate architecture to achieve high-speed operation.It is internally configured as an eight bank DRAM.

    DDR3
  • DDR3 ( H3I2G16LFG-RDA )

    The 2Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

    DDR3
  • DDR3 ( H3I4G16LFG-RDA )

    The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

    DDR3
  • DDR3 ( H3I1G08LFG-RDC )

    The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

    DDR3
  • DDR3 ( H3I2G08LFG-RDC )

    The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is double data rate architecture to achieve high-speed operation.It is internally configured as an eight bank DRAM.

    DDR3
  • DDR3 ( H3I4G08LFG-TEC )

    The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

    DDR3
  • DDR4( H4I4G16BLF-UKC )

    256M x 16 bit DDR4 Synchronous DRAM (SDRAM).

    DDR4
  • DDR4( H4I8G16BLF-UKC )

    512M x 16 bit DDR4 Synchronous DRAM (SDRAM).

    DDR4
  • LPDDR4 ( H4IBE3S4HR-THCL )

    UFS Memory and Mobile LPDDR4X 254-Ball MCP.

    LPDDR4
  • LPDDR4 ( 200BALL 2GB SDRAM )

    Thisdatasheetspecifiestheoperationoftheunified LPDDR4 and LPDDR4X product, and first describes specific requirements for LPDDR4X 0.6V VDDQ operation. When using the product as an LPDDR4 device,refer to LPDDR4 setting section LPDDR4 1.10V VDDQ at the end of this data sheet.

    LPDDR4
  • LPDDR4 ( UMCP 128+32)

    Thisdatasheetspecifiestheoperationoftheunified LPDDR4 and LPDDR4X product, and first describes specific requirements for LPDDR4X 0.6V VDDQ operation. When using the product as an LPDDR4 device,refer to LPDDR4 setting section LPDDR4 1.10V VDDQ at the end of this data sheet.

    LPDDR4

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