The H2I1G16KFR is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random- access memory (SDRAM) containing 1024 Mbits in a 16-bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency,Write latency = Read latency -1, Off-Chip Driver (OCD)impedance adjustment, and On Die Termination(ODT).

DDR2

The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is double data rate architecture to achieve high-speed operation.It is internally configured as an eight bank DRAM.

DDR3

The 2Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

DDR3

The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

DDR3

The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

DDR3

The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is double data rate architecture to achieve high-speed operation.It is internally configured as an eight bank DRAM.

DDR3

The 4Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.

DDR3

256M x 16 bit DDR4 Synchronous DRAM (SDRAM).

DDR4

512M x 16 bit DDR4 Synchronous DRAM (SDRAM).

DDR4

UFS Memory and Mobile LPDDR4X 254-Ball MCP.

LPDDR4

Thisdatasheetspecifiestheoperationoftheunified LPDDR4 and LPDDR4X product, and first describes specific requirements for LPDDR4X 0.6V VDDQ operation.

LPDDR4

Thisdatasheetspecifiestheoperationoftheunified LPDDR4 and LPDDR4X product, and first describes specific requirements for LPDDR4X 0.6V VDDQ operation.

LPDDR4