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DDR4(H4I8G16BLF-UKC)

一、Features

  • JEDEC Standard Compliant;
  • Fast clock rate: 1200/1333/1600MHz;
  • Power supplies:
  • — VDD & VDDQ = +1.2V ± 0.06V
  • — VPP = +2.5V -0.125V / +0.25V
  • Operating temperature: TC = -40~95°C (Industrial);
  • Supports JEDEC clock jitter specification;
  • Bidirectional differential data strobe, DQS &DQS#;
  • Differential Clock, CK & CK#;
  • 8 internal banks: 2 groups of 4 banks each;
  • Separated IO gating structures by Bank Group;
  • 8n-bit prefetch architecture;
  • Precharge & Active power down;
  • Auto Refresh and Self Refresh;
  • Low-power auto self refresh (LPASR);
  • Self Refresh Abort;
  • Fine Granularity Refresh;
  • Dynamic ODT (RTT_PARK & RTT_Nom & RTT_WR);
  • Write Leveling;
  • DQ Training via MPR;
  • Programmable preamble is supported both of 1tCK and 2tCK mode;
  • Command/Address (CA) Parity;
  • Data bus write cyclic redundancy check (CRC);
  • Boundary Scan Mode;
  • Internal VREFDQ Training;
  • Read Preamble Training;
  • Control Gear Down Mode;
  • Per DRAM Addressability (PDA);
  • Output Driver Impedance Control;
  • Dynamic on-die termination (ODT);
  • Input Data Mask (DM) andData Bus Inversion (DBI);
  • ZQ Calibration;
  • Command/Address latency (CAL);
  • Asynchronous Reset;
  • DLL enable/disable;
  • Burst Length (BL8/BC4/BC4 or 8 on the fly);
  • Burst type: Sequential / Interleave;
  • CAS Latency (CL);
  • CAS Write Latency (CWL);
  • Additive Latency (AL): 0, CL-1, CL-2;
  • Average refresh period;
  • — 8192 cycles/64ms (7.8μs at -40°C ≤ TC ≤ +85°C)
  • — 8192 cycles/32ms (3.9μs at +85°C ≤ TC ≤ +95°C)
  • Data Interface: Pseudo Open Drain (POD);
  • RoHS compliant;
  • Hard post package repair (hPPR);
  • Soft post package repair (sPPR);
  • Package: Pb Free and Halogen Free;
  • — 96-ball 7.5 x 13.5 x 1.2mm FBGA

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